The present invention relates to a method and apparatus for testing a non-volatile memory array and more particularly for testing a non-volatile memory array of the type having a low number of output pins, such as a non-volatile memory array having a serial output of data.
Non-volatile memory devices are well-known in the art. In the prior art, to test the memory cells of a non-volatile memory array in the device, the tester typically writes data having a test pattern into the non-volatile memory device. The memory cells which store the test pattern are then read out of the device and are then compared to the expected test pattern. If the comparison shows a flaw, then certain of the memory cells of the memory array in the device are flawed.
Because the testing of the memory cells of a non-volatile memory device involves the writing of a number of different test pattern data into the memory and then reading the data out, the testing of the memory cells of a non-volatile memory array is one of the bottlenecks.
The bottleneck for testing the memory cells of a non-volatile memory array is further exacerbated if the memory device is one that has a low pin output count, such as a serial device. In a serial device, typically, one data pin output is provided and data from the memory cells of the memory array must be read out serially. In a typical test procedure to test the memory cells of a serial output non-volatile memory device, the bit data is serially outputted from the memory device one at a time until an entire byte is read out with the byte of data preceded and followed an acknowledgment signal. Thus, due to the limited access of data from the memory device to the outside world of tester, this creates a bottleneck to the high speed testing of the non-volatile memory device.
Accordingly, in the present Invention, a method and apparatus are provided to test a non-volatile memory device. The non-volatile memory device has an array of non-volatile memory cells which are arranged in a plurality of columns and rows. A plurality of sense amplifiers are provided with one associated with each column. Each of the sense amplifiers receives the signal read from a memory cell in the associated column. A plurality of latches for storing a plurality of test signals are also provided. A plurality of comparators are also provided. One comparator is associated with each latch and with each sense amplifier for receiving the signals therefrom and for comparing same and for generating a test result signal. A logic circuit receives a plurality of the test result signals which are the outputs of the plurality of comparators and generates an output signal in response thereto. The output signal is supplied on an output pin.